// Cell names have been changed in this file by netl_namemap on Mon Jan  3 04:00:14 UTC 2022
////////////////////////////////////////////////////////////////////////////// 
//
//  pcs_raw_irq_ctl.v
//
//  Interrupt Request control
//
//  Original Author: Ameer Youssef 
//  Current Owner:   Gaurav Dubey   
//
////////////////////////////////////////////////////////////////////////////// 
//
// Copyright (C) 2015 Synopsys, Inc.  All rights reserved.
//
// SYNOPSYS CONFIDENTIAL - This is an unpublished, proprietary work of
// Synopsys, Inc., and is fully protected under copyright and trade secret
// laws.  You may not view, use, disclose, copy, or distribute this file or
// any information contained herein except pursuant to a valid written
// license agreement. It may not be used, reproduced, or disclosed to others
// except in accordance with the terms and conditions of that agreement.
//
////////////////////////////////////////////////////////////////////////////// 
//
//    Perforce Information
//    $Author: gdube $
//    $File: //dwh/up16/main/dev/pcs_raw/dig/rtl/pcs_raw_irq_ctl.v $
//    $DateTime: 2019/09/28 22:05:13 $
//    $Revision: #22 $
//
////////////////////////////////////////////////////////////////////////////// 

`include "dwc_e12mp_phy_x4_ns_pcs_raw_macros.v"

`timescale 1ns/10fs
module dwc_e12mp_phy_x4_ns_pcs_raw_irq_ctl (
// Clocks and resets
input  wire          cr_clk,
input  wire          cr_rst,

// Asynchronous interrupt sources
input  wire          rx_reset_i,
input  wire          rx_req_i,
input  wire [1:0]    rx_rate_i,
input  wire [1:0]    rx_width_i,
input  wire [5:0]    rx_ref_ld_val_i,
input  wire [12:0]   rx_vco_ld_val_i,
input  wire          rx_cdr_vco_lowfreq_i,
input  wire [1:0]    rx_pstate_i,
input  wire          rx_adapt_req_i,

`ifdef DWC_E12MP_X4NS_RX_CDR_PPM_DETECTOR_ADDED
// Synchronous interrupt sources
output wire          rx_adapt_req_sync,
`endif

// Interrupt mask clear
input  wire          irq_msk_clr,

// Combined interrupt request
output wire          irq,

// SCAN interface                     
input  wire          scan_mode_i,
input  wire          scan_set_rst_i,

// CREG interface (accessing CREGs in this block)                     
output wire [15:0]   cr_rd_data,
input  wire [15:0]   cr_wr_data,
input  wire          cr_wr_en,
input  wire [13:0]   cr_sel
);

// -------------------------
// Registers and nets
// -------------------------

reg  [2:0] init_cnt;
wire       disable_irq;

// sync'ed interrupt sources
wire       rx_reset_sync;
wire       rx_req_sync;
`ifndef DWC_E12MP_X4NS_RX_CDR_PPM_DETECTOR_ADDED
wire       rx_adapt_req_sync;
`endif

// interrupt requests
wire       rx_reset_irq;
wire       rx_req_irq;
wire       rx_rate_irq;
wire       rx_pstate_irq;
wire       rx_adapt_req_irq;
wire       rx_adapt_dis_irq;

// interrupt mask registers
wire       rx_req_irq_msk_r;
wire       rx_rate_irq_msk_r;
wire       rx_pstate_irq_msk_r;
wire       rx_adapt_req_irq_msk_r;
wire       rx_adapt_dis_irq_msk_r;
wire       rx_reset_irq_msk_r;

// interrupt clear registers
wire       rx_reset_irq_clr_r;
wire       rx_req_irq_clr_r;
wire       rx_rate_irq_clr_r;
wire       rx_pstate_irq_clr_r;
wire       rx_adapt_req_irq_clr_r;
wire       rx_adapt_dis_irq_clr_r;

// ---------------------------------------
// Generate common interrupt using masks
// ---------------------------------------
assign irq = (rx_req_irq       & rx_req_irq_msk_r      ) |
             (rx_rate_irq      & rx_rate_irq_msk_r     ) | 
             (rx_pstate_irq    & rx_pstate_irq_msk_r   ) | 
             (rx_adapt_req_irq & rx_adapt_req_irq_msk_r) | 
             (rx_adapt_dis_irq & rx_adapt_dis_irq_msk_r) |
             (rx_reset_irq     & rx_reset_irq_msk_r);
    
// -------------------------
// Synchronize Inputs
// -------------------------
// Mantis 7139 - Send rx_reset to a pcs_raw_gen_rst_sync first so that
// the pulse can always be captured regardless of how wide it is
// Note that to prevent C-26 DFt violations, we mux in a different
// value during scan mode or else the reset is captured by the
// ATPG flop in the pcs_raw_gen_rst_sync
wire rx_reset_int1;
dwc_e12mp_phy_x4_ns_gen_mux rx_reset_irq_mux1 (
  .out (rx_reset_int1),
  .sel (scan_mode_i),
  .d0  (rx_reset_i),
  .d1  (init_cnt[0])
);

wire rx_reset_extended;
dwc_e12mp_phy_x4_ns_pcs_raw_gen_rst_sync #(.ATPG_COV(0)) rx_reset_irq_rst_sync (
  .sync_rst       (rx_reset_extended),
  .clk            (cr_clk),
  .async_rst      (rx_reset_int1),
  .scan_mode_i    (scan_mode_i),
  .scan_set_rst_i (scan_set_rst_i)
);

// Mantis 6810 - 
// In scan mode, rx_reset_i will have scan muxed onto it, and therefore
// cannot be sent to a synchronizer directly.  Instead send an arbitrary
// register on the same clock domain in scan mode to maintain coverage.
wire rx_reset_int2;
dwc_e12mp_phy_x4_ns_gen_mux rx_reset_irq_mux (
  .out (rx_reset_int2),
  .sel (scan_mode_i),
  .d0  (rx_reset_extended),
  .d1  (init_cnt[0])
);

dwc_e12mp_phy_x4_ns_gen_sync sync_rx_reset (
  .q   (rx_reset_sync),
  .clk (cr_clk),
  .rst (cr_rst),
  .d   (rx_reset_int2)
);

dwc_e12mp_phy_x4_ns_gen_sync sync_rx_req (
  .q   (rx_req_sync),
  .clk (cr_clk),
  .rst (cr_rst),
  .d   (rx_req_i)
);

dwc_e12mp_phy_x4_ns_gen_sync sync_rx_adapt_req (
  .q   (rx_adapt_req_sync),
  .clk (cr_clk),
  .rst (cr_rst),
  .d   (rx_adapt_req_i)
);

// -------------------------------
// Disable interrupts out of reset
// -------------------------------
// Comming out of reset should not trigger an interrupt
// if the value is different than the reset value, this
// is expected and not an interrupt.
always @(posedge cr_clk or posedge cr_rst) begin
  if (cr_rst)
    init_cnt <= 3'd7;
  else if (init_cnt != 3'd0)
    init_cnt <= init_cnt - 3'd1;
end
assign disable_irq = (init_cnt != 3'd0);

// -------------------------------
// Trigger Interrupts
// -------------------------------

// Assertion of rx_reset interrupt request
dwc_e12mp_phy_x4_ns_pcs_raw_irq_gen rx_reset_irq_gen (
  .irq   (rx_reset_irq),
  .clk   (cr_clk),
  .rst   (cr_rst),
  .sclr  (rx_reset_irq_clr_r | disable_irq),
  .en    (1'b1),
  .d     (rx_reset_sync)
);

// Assertion of rx_req interrupt request
dwc_e12mp_phy_x4_ns_pcs_raw_irq_gen rx_req_irq_gen (
  .irq   (rx_req_irq),
  .clk   (cr_clk),
  .rst   (cr_rst),
  .sclr  (rx_req_irq_clr_r | disable_irq),
  .en    (1'b1),
  .d     (rx_req_sync)
);

// Rate change interrupt request
dwc_e12mp_phy_x4_ns_pcs_raw_irq_gen #(.WIDTH(24),.ANY_EDGE(1),.ASYNC_D(1)) rx_rate_irq_gen (
  .irq   (rx_rate_irq),
  .clk   (cr_clk),
  .rst   (cr_rst),
  .sclr  (rx_rate_irq_clr_r | disable_irq),
  .en    (rx_req_sync | disable_irq),
  .d     ({rx_rate_i,rx_width_i,rx_cdr_vco_lowfreq_i,rx_ref_ld_val_i,rx_vco_ld_val_i})
);

// Pstate change interrupt request
dwc_e12mp_phy_x4_ns_pcs_raw_irq_gen #(.WIDTH(2),.ANY_EDGE(1),.ASYNC_D(1)) rx_pstate_irq_gen (
  .irq   (rx_pstate_irq),
  .clk   (cr_clk),
  .rst   (cr_rst),
  .sclr  (rx_pstate_irq_clr_r | disable_irq),
  .en    (rx_req_sync | disable_irq),
  .d     (rx_pstate_i)
);

// Assertion of rx_adapt_req interrupt request
dwc_e12mp_phy_x4_ns_pcs_raw_irq_gen rx_adapt_req_irq_gen (
  .irq   (rx_adapt_req_irq),
  .clk   (cr_clk),
  .rst   (cr_rst),
  .sclr  (rx_adapt_req_irq_clr_r | disable_irq),
  .en    (1'b1),
  .d     (rx_adapt_req_sync)
);

// Deassertion of rx_adapt_req interrupt request
dwc_e12mp_phy_x4_ns_pcs_raw_irq_gen #(.FALLING_EDGE(1)) rx_adapt_dis_irq_gen (
  .irq   (rx_adapt_dis_irq),
  .clk   (cr_clk),
  .rst   (cr_rst),
  .sclr  (rx_adapt_dis_irq_clr_r),
  .en    (1'b1),
  .d     (rx_adapt_req_sync)
);


// -------------------------------
// Routine Request registers
// -------------------------------

// -------------------------------------------------------------------------
// %%CREG RESET_RTN_REQ - Reset routine request
//   OFFSET: 0x0
//   ATTR: READ,WRITE
//   FIELDS:
//      [0] RESET_RTN_REQ    - Reset routine request
//          RESET: 0x1
// ---------------------------------------------------------------------
wire reset_rtn_req_r;
wire [15:0] cr_reset_rtn_req_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(1), .RST_VAL(1'b1), .MSK_VAL(1'b0)) 
 reset_rtn_req_reg (
  .cr_val      (reset_rtn_req_r),
  .cr_rd_data  (cr_reset_rtn_req_rd_data),
  .cr_wr_data  (cr_wr_data),
  .cr_wr_en    (cr_wr_en),
  .cr_clk      (cr_clk),
  .cr_rst      (cr_rst),
  .cr_sel      (cr_sel[0]),
  .cr_self_clr (1'b0)
);

// -------------------------------------------------------------------------
// %%CREG RX_RESET_IRQ - Rx reset interrupt
//   OFFSET: 0x1
//   ATTR: READ
//   FIELDS:
//       [0] RX_RESET    - Rx reset interrupt
// -------------------------------------------------------------------------
wire [15:0] cr_rx_reset_rd_data;
dwc_e12mp_phy_x4_ns_cr_r_reg #(.WIDTH(1)) rx_reset_reg (
  .cr_rd_data (cr_rx_reset_rd_data),
  .cr_sel     (cr_sel[1]),
  .cr_val     (rx_reset_irq)
);

// -------------------------------------------------------------------------
// %%CREG RX_REQ_IRQ - Rx request interrupt
//   OFFSET: 0x2
//   ATTR: READ
//   FIELDS:
//       [0] RX_REQ    - Rx request interrupt
// -------------------------------------------------------------------------
wire [15:0] cr_rx_req_rd_data;
dwc_e12mp_phy_x4_ns_cr_r_reg #(.WIDTH(1)) rx_req_reg (
  .cr_rd_data (cr_rx_req_rd_data),
  .cr_sel     (cr_sel[2]),
  .cr_val     (rx_req_irq)
);

// -------------------------------------------------------------------------
// %%CREG RX_RATE_IRQ - Rx rate change interrupt request
//   OFFSET: 0x3
//   ATTR: READ
//   FIELDS:
//       [0] RX_RATE_IRQ    - Rx rate change interrupt request
// -------------------------------------------------------------------------
wire [15:0] cr_rx_rate_irq_rd_data;
dwc_e12mp_phy_x4_ns_cr_r_reg #(.WIDTH(1)) rx_rate_irq_reg (
  .cr_rd_data (cr_rx_rate_irq_rd_data),
  .cr_sel     (cr_sel[3]),
  .cr_val     (rx_rate_irq)
);

// -------------------------------------------------------------------------
// %%CREG RX_PSTATE_IRQ - Rx pstate change interrupt request
//   OFFSET: 0x4
//   ATTR: READ
//   FIELDS:
//       [0] RX_PSTATE_IRQ    - Rx pstate change interrupt request
// -------------------------------------------------------------------------
wire [15:0] cr_rx_pstate_irq_rd_data;
dwc_e12mp_phy_x4_ns_cr_r_reg #(.WIDTH(1)) rx_pstate_irq_reg (
  .cr_rd_data (cr_rx_pstate_irq_rd_data),
  .cr_sel     (cr_sel[4]),
  .cr_val     (rx_pstate_irq)
);

// -------------------------------------------------------------------------
// %%CREG RX_ADAPT_REQ_IRQ - Rx adaptation request interrupt
//   OFFSET: 0x5
//   ATTR: READ
//   FIELDS:
//       [0] RX_ADAPT_REQ_IRQ    - Rx adaptation request interrupt
// -------------------------------------------------------------------------
wire [15:0] cr_rx_adapt_req_irq_rd_data;
dwc_e12mp_phy_x4_ns_cr_r_reg #(.WIDTH(1)) rx_adapt_req_irq_reg (
  .cr_rd_data (cr_rx_adapt_req_irq_rd_data),
  .cr_sel     (cr_sel[5]),
  .cr_val     (rx_adapt_req_irq)
);

// -------------------------------------------------------------------------
// %%CREG RX_ADAPT_DIS_IRQ - Rx adaptation disable interrupt
//   OFFSET: 0x6
//   ATTR: READ
//   FIELDS:
//       [0] RX_ADAPT_DIS_IRQ    - Rx adaptation disable interrupt
// -------------------------------------------------------------------------
wire [15:0] cr_rx_adapt_dis_irq_rd_data;
dwc_e12mp_phy_x4_ns_cr_r_reg #(.WIDTH(1)) rx_adapt_dis_irq_reg (
  .cr_rd_data (cr_rx_adapt_dis_irq_rd_data),
  .cr_sel     (cr_sel[6]),
  .cr_val     (rx_adapt_dis_irq)
);

// -------------------------------
// Interrupt Clear Registers
// -------------------------------

// -------------------------------------------------------------------------
// %%CREG RX_RESET_IRQ_CLR - RX reset interrupt clear
//   OFFSET: 0x7
//   ATTR: READ,WRITE
//   FIELDS:
//      [0] RX_RESET_IRQ_CLR    - RX reset interrupt clear (self-clearing)
//          RESET: 0x0
// ---------------------------------------------------------------------
wire [15:0] cr_rx_reset_irq_clr_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(1), .RST_VAL(1'b0), .MSK_VAL(1'b1)) 
 rx_reset_irq_clr_reg (
  .cr_val      (rx_reset_irq_clr_r),
  .cr_rd_data  (cr_rx_reset_irq_clr_rd_data),
  .cr_wr_data  (cr_wr_data),
  .cr_wr_en    (cr_wr_en),
  .cr_clk      (cr_clk),
  .cr_rst      (cr_rst),
  .cr_sel      (cr_sel[7]),
  .cr_self_clr (rx_reset_irq_clr_r)
);

// -------------------------------------------------------------------------
// %%CREG RX_REQ_IRQ_CLR - RX request interrupt clear
//   OFFSET: 0x8
//   ATTR: READ,WRITE
//   FIELDS:
//      [0] RX_REQ_IRQ_CLR    - RX request interrupt clear (self-clearing)
//          RESET: 0x0
// ---------------------------------------------------------------------
wire [15:0] cr_rx_req_irq_clr_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(1), .RST_VAL(1'b0), .MSK_VAL(1'b1)) 
 rx_req_irq_clr_reg (
  .cr_val      (rx_req_irq_clr_r),
  .cr_rd_data  (cr_rx_req_irq_clr_rd_data),
  .cr_wr_data  (cr_wr_data),
  .cr_wr_en    (cr_wr_en),
  .cr_clk      (cr_clk),
  .cr_rst      (cr_rst),
  .cr_sel      (cr_sel[8]),
  .cr_self_clr (rx_req_irq_clr_r)
);

// -------------------------------------------------------------------------
// %%CREG RX_RATE_IRQ_CLR - RX rate change interrupt clear
//   OFFSET: 0x9
//   ATTR: READ,WRITE
//   FIELDS:
//      [0] RX_RATE_IRQ_CLR    - RX rate change interrupt clear (self-clearing)
//          RESET: 0x0
// ---------------------------------------------------------------------
wire [15:0] cr_rx_rate_irq_clr_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(1), .RST_VAL(1'b0), .MSK_VAL(1'b1)) 
 rx_rate_irq_clr_reg (
  .cr_val      (rx_rate_irq_clr_r),
  .cr_rd_data  (cr_rx_rate_irq_clr_rd_data),
  .cr_wr_data  (cr_wr_data),
  .cr_wr_en    (cr_wr_en),
  .cr_clk      (cr_clk),
  .cr_rst      (cr_rst),
  .cr_sel      (cr_sel[9]),
  .cr_self_clr (rx_rate_irq_clr_r)
);

// -------------------------------------------------------------------------
// %%CREG RX_PSTATE_IRQ_CLR - RX pstate change interrupt clear
//   OFFSET: 0xA
//   ATTR: READ,WRITE
//   FIELDS:
//      [0] RX_PSTATE_IRQ_CLR    - RX pstate change interrupt clear (self-clearing)
//          RESET: 0x0
// ---------------------------------------------------------------------
wire [15:0] cr_rx_pstate_irq_clr_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(1), .RST_VAL(1'b0), .MSK_VAL(1'b1)) 
 rx_pstate_irq_clr_reg (
  .cr_val      (rx_pstate_irq_clr_r),
  .cr_rd_data  (cr_rx_pstate_irq_clr_rd_data),
  .cr_wr_data  (cr_wr_data),
  .cr_wr_en    (cr_wr_en),
  .cr_clk      (cr_clk),
  .cr_rst      (cr_rst),
  .cr_sel      (cr_sel[10]),
  .cr_self_clr (rx_pstate_irq_clr_r)
);

// -------------------------------------------------------------------------
// %%CREG RX_ADAPT_REQ_IRQ_CLR - RX adaptation request interrupt clear
//   OFFSET: 0xB
//   ATTR: READ,WRITE
//   FIELDS:
//      [0] RX_ADAPT_REQ_IRQ_CLR    - RX adaptation request interrupt clear (self-clearing)
//          RESET: 0x0
// ---------------------------------------------------------------------
wire [15:0] cr_rx_adapt_req_irq_clr_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(1), .RST_VAL(1'b0), .MSK_VAL(1'b1)) 
 rx_adapt_req_irq_clr_reg (
  .cr_val      (rx_adapt_req_irq_clr_r),
  .cr_rd_data  (cr_rx_adapt_req_irq_clr_rd_data),
  .cr_wr_data  (cr_wr_data),
  .cr_wr_en    (cr_wr_en),
  .cr_clk      (cr_clk),
  .cr_rst      (cr_rst),
  .cr_sel      (cr_sel[11]),
  .cr_self_clr (rx_adapt_req_irq_clr_r)
);

// -------------------------------------------------------------------------
// %%CREG RX_ADAPT_DIS_IRQ_CLR - RX adaptation disable interrupt clear
//   OFFSET: 0xC
//   ATTR: READ,WRITE
//   FIELDS:
//      [0] RX_ADAPT_DIS_IRQ_CLR    - RX adaptation disable interrupt clear (self-clearing)
//          RESET: 0x0
// ---------------------------------------------------------------------
wire [15:0] cr_rx_adapt_dis_irq_clr_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(1), .RST_VAL(1'b0), .MSK_VAL(1'b1)) 
 rx_adapt_dis_irq_clr_reg (
  .cr_val      (rx_adapt_dis_irq_clr_r),
  .cr_rd_data  (cr_rx_adapt_dis_irq_clr_rd_data),
  .cr_wr_data  (cr_wr_data),
  .cr_wr_en    (cr_wr_en),
  .cr_clk      (cr_clk),
  .cr_rst      (cr_rst),
  .cr_sel      (cr_sel[12]),
  .cr_self_clr (rx_adapt_dis_irq_clr_r)
);

// -------------------------------------------------------------------------
// %%CREG IRQ_MASK - Interrupt Mask
//   OFFSET: 0xD
//   ATTR: READ,WRITE
//   FIELDS:
//      [5] RX_RESET_IRQ_MSK      - Mask for Rx reset interrupt (0 = cannot interrupt)
//          RESET: 0x0
//      [4] RX_ADAPT_DIS_IRQ_MSK  - Mask for Rx adaptation disable interrupt (0 = cannot interrupt)
//          RESET: 0x0
//      [3] RX_ADAPT_REQ_IRQ_MSK  - Mask for Rx adaptation request interrupt (0 = cannot interrupt)
//          RESET: 0x0
//      [2] RX_PSTATE_IRQ_MSK     - Mask for Rx pstate change interrupt (0 = cannot interrupt)
//          RESET: 0x0
//      [1] RX_RATE_IRQ_MSK       - Mask for Rx rate change interrupt (0 = cannot interrupt)
//          RESET: 0x0
//      [0] RX_REQ_IRQ_MSK        - Mask for Rx request interrupt (0 = cannot interrupt)
//          RESET: 0x0
// ---------------------------------------------------------------------
wire [15:0] cr_irq_msk_rd_data;
dwc_e12mp_phy_x4_ns_cr_rw_reg #(.WIDTH(6), .RST_VAL(6'b000000), .MSK_VAL(6'b111111)) 
 irq_msk_reg (
  .cr_val      ({
                 rx_reset_irq_msk_r,
                 rx_adapt_dis_irq_msk_r,
                 rx_adapt_req_irq_msk_r,
                 rx_pstate_irq_msk_r,
                 rx_rate_irq_msk_r,
                 rx_req_irq_msk_r
                 }),
  .cr_rd_data  (cr_irq_msk_rd_data),
  .cr_wr_data  (cr_wr_data),
  .cr_wr_en    (cr_wr_en),
  .cr_clk      (cr_clk),
  .cr_rst      (cr_rst),
  .cr_sel      (cr_sel[13]),
  .cr_self_clr (irq_msk_clr)
);

// Muxed register read for CREG register
//     
assign cr_rd_data = cr_reset_rtn_req_rd_data        |
                    cr_rx_reset_rd_data             |
                    cr_rx_req_rd_data               |
                    cr_rx_rate_irq_rd_data          |
                    cr_rx_pstate_irq_rd_data        |
                    cr_rx_adapt_req_irq_rd_data     |
                    cr_rx_adapt_dis_irq_rd_data     |
                    cr_rx_reset_irq_clr_rd_data     |
                    cr_rx_req_irq_clr_rd_data       |
                    cr_rx_rate_irq_clr_rd_data      |
                    cr_rx_pstate_irq_clr_rd_data    |
                    cr_rx_adapt_req_irq_clr_rd_data |
                    cr_rx_adapt_dis_irq_clr_rd_data |
                    cr_irq_msk_rd_data;

endmodule

